1. Field of the Invention
The invention relates to memory and more particularly to memory with changeable resistance.
2. Description of the Related Art
Non-volatile Magnetic Random Access Memory (MRAM), unlike memory which stores data in the form of charge or current, stores data with magnetic storage cells. Because MRAM provides high cell density and access speed, it gained popularity in memory fabrication.
FIG. 1 shows a conventional MRAM cell 100 comprising a transistor 102 and two Magnetic Tunnel Junction (MTJ) devices 104 and 106. The MTJ devices 104 and 106 are coupled in parallel between a read bit line RBL and a node 108. MTJ devices typically comprise a plurality of interleaved ferromagnetic layers and insulating layers. A magnetic field applied to the MRAM cell 100 shifts the polarity of the ferromagnetic layers, changing the resistance of the MTJ devices 104 and 106. Thus, the MTJ devices 104 and 106 can be switched between two levels of resistance.
A transistor 102 is coupled between the node 108 and a ground. The gate of the transistor 102 is coupled to a word line WL. When a high voltage is applied to the word line WL to turn on the transistor 102, the MTJ devices 104 and 106 are connected in parallel between the read bit line RBL and ground. The read bit line RBL is biased by a constant voltage and coupled to a sense amplifier, such that current level through the read bit line RBL changes with the resistance of the MTJ devices 104 and 106. The sense amplifier can then read data stored in MRAM cell 100 by detecting the current level. Because the sizes of the two MTJ devices 104 and 106 are different, the changeable resistance level of the MTJ devices is also different. For example, if the MTJ device 104 can be switched between resistance level R1max and R1min, and the MTJ device 106 can be switched between resistance level R2max and R2min, the total resistance of the MRAM cell 100 can then be switched among four levels of R1max//R2max, R1max//R2min, R1min//R2max, and R1min//R2min. Accordingly, the MRAM cell 100 has four memory states, each capable of storing 2 bits of data. FIG. 2 is a table 200 showing the relationship between the resistance level of the MRAM cell 100 and corresponding data stored in the MRAM cell 100. The data stored in the MRAM cell 100 is respectively 11, 10, 01, and 00.
Because an MRAM comprises a plurality of MRAM cells 100, an output circuit must be coupled to the bit line to detect data stored in a specific MRAM cell. The design of the output circuit heavily affects access time and performance of the MRAM. If an output circuit detects the current or voltage of the bit line with a multi-state sense amplifier, the access time is greatly reduced and the performance of the MRAM improved.
The multiple bit lines and word lines of a memory induce parasitic capacitance. When a memory cell is turned on, the memory cell is directly coupled to the multi-state sense amplifier, and the voltage drops across the MTJ devices induce a current along the path between the memory cell and the multi-state sense amplifier. According to the charge conservation theorem Q=C×V=I×t, when the memory cell is turned on, the current cannot immediately charge the parasitic capacitance coupled to the current path to force the transistors of the sense amplifier into triode regions, and the output voltage of the sense amplifier is pulled up to a logic high level, increasing the access time of the MRAM.
A method is thus provided for ameliorating the described problems. The method couples the output terminals of reference cells to switches to be turned on only when the memory cell is turned on to clamp the voltage of the output terminals of the reference cells to a certain voltage. Thus, the voltages of transistors of the sense amplifier are prevented from being pulled up to the logic high level reducing access time by half.